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SST34HF1641J
16 Mbit Concurrent SuperFlash + 4/8 Mbit PSRAM ComboMemory
The SST34HF1641J ComboMemory integrates either a 1M x16 or 2M x8 CMOS flash memory bank with either a 256K x16, or 512K x16 CMOS pseudo SRAM (PSRAM) memory bank in a multi-chip package (MCP). This device is fabricated using SST proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick-oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF1641J is ideal for applications such as cellular phones, GPS devices, PDAs, and other portable electronic devices in a low power and small form factor system.
The SST34HF1641J features dual flash memory bank architecture allowing for concurrent operations between the two flash memory banks and the PSRAM. The device can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The two flash memory banks are partitioned into 12 Mbit and 4 Mbit with bottom sector protection options for storing boot code, program code, configuration/parameter data and user data.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The SST34HF1641J offers a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. With high-performance Program operations, the flash memory banks provide a typical Word-Program time of 7 µsec.To protect against inadvertent flash write, the SST34HF1641J contains on-chip hardware and software data protection schemes. The flash and PSRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The PSRAM bank enable signals, BES1# and BES2, select the PSRAM bank. The flash memory bank enable signal, BEF#, has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area.
Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF1641J is offered in extended temperatures and a small footprint package to meet board space constraint requirements.
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