The SST32HF64A2 ComboMemory device integrates a  CMOS flash memory bank with a CMOS PseudoSRAM  (PSRAM) memory bank in a Multi-Chip Package (MCP),  manufactured with SST proprietary, high-performance  SuperFlash technology.

Featuring high-performance Word-Program, the flash  memory bank provides a maximum Word-Program time of  7 µsec. To protect against inadvertent flash write, the  SST32HF64A2 device contains on-chip hardware and software  data protection schemes. The SST32HF64A2 device  offers a guaranteed endurance of 10,000 cycles, and data  retention greater than 100 years.

The SST32HF64A2 device consists of two independent  memory banks, each with enable signals. The flash and  PSRAM memory banks are superimposed in the same  memory address space, and both banks share common  address lines, data lines, WE# and OE#. The memory  bank is selected using the memory bank enable signals.  The PSRAM bank enable signal, BES1#, selects the  PSRAM bank. The flash memory bank enable signal,  BEF#, selects the flash memory bank. The WE# signal is  used with the Software Data Protection (SDP) command  sequence when controlling the Erase and Program operations  in the flash memory bank. The SDP command  sequence protects the data stored in the flash memory  bank from accidental alteration.

The SST32HF64A2 provides the added functionality of  being able to simultaneously read from, or write to, the  PSRAM bank while erasing or programming in the flash  memory bank. The PSRAM memory bank can be read or  written while the flash memory bank performs Sector-  Erase, Bank-Erase, or Word-Program concurrently. All  flash memory Erase and Program operations will automatically  latch the input address and data signals and complete  the operation in background without further input stimulus  required. Once the internally controlled Erase or Program  cycle in the flash bank commences, the PSRAM bank can  be accessed for Read or Write.